The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structure.
In the past, the semiconductor industry utilized various structures and methods to form vertical power transistors on the same substrate with other transistors such as lateral transistors. Forming a vertical power transistor on the same semiconductor die with other transistors was highly desirable and offered designers the flexibility to combine various functions on a single semiconductor die. However, it was difficult to provide a low on-resistance for the vertical power transistor. Typically, the other transistors required a lightly doped semiconductor region in which to form the other transistors. This light doping increased the on-resistance of the vertical power transistor.
Accordingly, it is desirable to have a vertical power transistor formed on the same substrate with other transistors and a vertical power transistor that has low on-resistance.
For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. Although the devices are explained herein as certain N-channel or P-Channel devices, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with the present invention. For clarity of the drawings, doped regions of device structures are illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that due to the diffusion and activation of dopants the edges of doped regions are generally not straight lines and the corners are not precise angles.